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16-bit, 1.5 lsb inl, 500 ksps pulsar? differential adc in msop/qfn ad7688 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007C2011 analog devices, inc. all rights reserved. features 16-bit resolution with no missing codes throughput: 500 ksps inl: 0.4 lsb typ, 1.5 lsb max (23 ppm of fsr) dynamic range: 96.5 db snr: 95.5 db @ 20 khz thd: ?118 db @ 20 khz true differential analog input range v ref 0 v to v ref with v ref up to vdd on both inputs no pipeline delay single-supply 5 v operation with 1.8 v/2.5 v/3 v/5 v logic interface serial interface spi?/qspi?/microwire?/dsp-compatible daisy-chain multiple adcs and busy indicator power dissipation 3.75 mw @ 5 v/100 ksps 3.75 w @ 5 v/100 sps standby current: 1 na 10-lead msop (msop-8 size) and 3 mm 3 mm qfn (lfcsp) (sot-23 size) pin-for-pin compatible with ad7685, ad7686, and ad7687 applications battery-powered equipment data acquisitions instrumentation medical instruments process controls code inl (lsb) 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 0 16384 32768 49152 65535 02973-001 positive inl = +0.31lsb negative inl = ?0.39lsb figure 1. integral nonlinearity vs. code application diagram ad7688 ref gnd vdd in+ in? vio sdi sck sdo cnv 1.8v to vdd 3- or 4-wire interface (spi, daisy chain, cs) 0.5v to 5v 5v vref 0 02973-002 vref 0 figure 2. table 1. msop, qfn (lfcsp)/sot-23 16-bit pulsar adc type 100 ksps 250 ksps 500 ksps true differential ad7684 ad7687 ad7688 pseudo ad7683 ad7685 ad7686 differential/unipolar ad7694 unipolar ad7680 general description the ad7688 is a 16-bit, charge redistribution, successive approximation, analog-to-digital converter (adc) that operates from a single 5 v power supply, vdd. it contains a low power, high speed, 16-bit sampling adc with no missing codes, an internal conversion clock, and a versatile serial interface port. the part also contains a low noise, wide bandwidth, short aperture delay track-and-hold circuit. on the cnv rising edge, it samples the voltage difference between in+ and in? pins. the voltages on these pins usually swing in opposite phase between 0 v and ref. the reference voltage, ref, is applied externally and can be set up to the supply voltage. its power scales linearly with throughput. the spi-compatible serial interface also features the ability, using the sdi input, to daisy-chain several adcs on a single, 3-wire bus and provides an optional busy indicator. it is compatible with 1.8 v, 2.5 v, 3 v, or 5 v logic, using the separate supply vio. the ad7688 is housed in a 10-lead msop or a 10-lead qfn (lfcsp) with operation specified from ?40c to +85c.
ad7688 rev. a | page 2 of 28 table of contents features .............................................................................................. 1 ? applications....................................................................................... 1 ? application diagram........................................................................ 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications..................................................................................... 3 ? timing specifications....................................................................... 5 ? absolute maximum ratings............................................................ 6 ? thermal resistance ...................................................................... 6 ? esd caution.................................................................................. 6 ? pin configuration and function descriptions............................. 7 ? terminology ...................................................................................... 8 ? typical performance characteristics ............................................. 9 ? circuit information.................................................................... 12 ? converter operation.................................................................. 12 ? typical connecti on diagram ................................................... 13 ? analog input ............................................................................... 14 ? driver amplifier choice ........................................................... 15 ? single-to-differential driver .................................................... 15 ? voltage reference input ............................................................ 15 ? power supply............................................................................... 15 ? supplying the adc from the reference.................................. 16 ? digital interface.......................................................................... 16 ? cs mode 3-wire, no busy indicator .................................. 17 ? cs mode 3-wire with busy indicator ................................... 18 ? cs mode 4-wire, no busy indicator..................................... 19 ? cs mode 4-wire with busy indicator ................................... 20 ? chain mode, no busy indicator ............................................ 21 ? chain mode with busy indicator........................................... 22 ? application hints ........................................................................... 23 ? layout .......................................................................................... 23 ? evaluating the ad7688s performance.................................... 23 ? outline dimensions ....................................................................... 24 ? ordering guide .......................................................................... 25 ? revision history 2/11rev. 0 to rev. a deleted qfn in development note............................ throughout changes to table 5............................................................................ 6 added thermal resistance section and table 6 .......................... 6 changes to figure 6 and table 7..................................................... 7 updated outline dimensions ....................................................... 24 changes to ordering guide .......................................................... 25 4/05revision 0: initial version
ad7688 rev. a | page 3 of 28 specifications vdd = 4.5 v to 5.5 v, vio = 2.3 v to vdd, v ref = vdd, t a = C40c to +85c, unless otherwise noted. table 2. parameter conditions min typ max unit resolution 16 bits analog input voltage range in+ ? in? ?v ref +v ref v absolute input voltage in+, in? ?0.1 v ref + 0.1 v common-mode input range in+, in? 0 v ref /2 v ref /2 + 0.1 v analog input cmrr f in = 250 khz 65 db leakage current at 25c acquisition phase 1 na input impedance see the analog input section accuracy no missing codes 16 bits differential linearity error ?1 0.4 +1 lsb 1 integral linearity error ?1.5 0.4 +1.5 lsb transition noise ref = vdd = 5 v 0.4 lsb gain error 2 , t min to t max 2 6 lsb gain error temperature drift 0.3 ppm/c zero error 2 , t min to t max 0.1 1.6 mv zero temperature drift 0.3 ppm/c power supply sensitivity vdd = 5v 5% 0.05 lsb throughput conversion rate 0 500 ksps transient response full-scale step 400 ns ac accuracy dynamic range v ref = 5 v 95.8 96.5 db 3 signal-to-noise f in = 20 khz, v ref = 5 v 94 95.5 db f in = 20 khz, v ref = 5 v 92.5 db spurious-free dynamic range f in = 20 khz ?118 db total harmonic distortion f in = 20 khz ?118 db signal-to-(noise + distortion) f in = 20 khz, v ref = 5 v 93.5 95 db f in = 20 khz, v ref = 5 v, ?60 db input 36.5 db intermodulation distortion 4 115 db 1 lsb means least significant bit. with the 5 v input range, one lsb is 152.6 v. 2 see the terminology section. these specific ations do include full temperature range variation but do not include the error con tribution from the external reference. 3 all specifications in db are referred to a full-scale input fs. tested with an input signal at 0.5 db below full-scale, unless otherwise specified. 4 f in1 = 21.4 khz, f in2 = 18.9 khz, each tone at ?7 db below full-scale.
ad7688 rev. a | page 4 of 28 vdd = 4.5 v to 5.5 v, vio = 2.3 v to vdd, v ref = vdd, t a = C40c to +85c, unless otherwise noted. table 3. parameter conditions min typ max unit reference voltage range 0.5 vdd + 0.3 v load current 500 ksps, ref = 5 v 100 a sampling dynamics ?3 db input bandwidth 9 mhz aperture delay vdd = 5 v 2.5 ns digital inputs logic levels v il C0.3 +0.3 vio v v ih 0.7 vio vio + 0.3 v i il ?1 +1 a i ih ?1 +1 a digital outputs data format serial 16 bits twos complement pipeline delay conversion results available immediately after completed conversion v ol i sink = +500 a 0.4 v v oh i source = ?500 a vio ? 0.3 v power supplies vdd specified performance 4.5 5.5 v vio specified performance 2.3 vdd + 0.3 v vio range 1.8 vdd + 0.3 v standby current 1 , 2 vdd and vio = 5 v, 25c 1 50 na power dissipation vdd = 5 v, 100 sps throughput 3.75 w vdd = 5 v, 100 ksps throughput 3.75 4.3 mw vdd = 5 v, 500 ksps throughput 21.5 mw temperature range 3 specified performance t min to t max ?40 +85 c 1 with all digital inputs forced to vio or gnd as required. 2 during acquisition phase. 3 contact sales for extended temperature range.
ad7688 rev. a | page 5 of 28 timing specifications ?40c to +85c, vdd = 4.5 v to 5.5 v, vio = 2.3 v to 5.5 v or vdd + 0.3 v, whichever is the lowest, unless otherwise stated. see figure 3 and figure 4 for load conditions. table 4. parameter symbol min typ max unit conversion time: cnv rising edge to data available t conv 0.5 1.6 s acquisition time t acq 400 ns time between conversions t cyc 2 s cnv pulse width ( cs mode ) t cnvh 10 ns sck period ( cs mode ) t sck 15 ns sck period ( chain mode ) t sck vio above 4.5 v 17 ns vio above 3 v 18 ns vio above 2.7 v 19 ns vio above 2.3 v 20 ns sck low time t sckl 7 ns sck high time t sckh 7 ns sck falling edge to data remains valid t hsdo 5 ns sck falling edge to data valid delay t dsdo vio above 4.5 v 14 ns vio above 3 v 15 ns vio above 2.7 v 16 ns vio above 2.3 v 17 ns cnv or sdi low to sdo d15 msb valid ( cs mode) t en vio above 4.5 v 15 ns vio above 2.7 v 18 ns vio above 2.3 v 22 ns cnv or sdi high or last sck falling edge to sdo high impedance ( cs mode) t dis 25 ns sdi valid setup time from cnv rising edge ( cs mode) t ssdicnv 15 ns sdi valid hold time from cnv rising edge ( cs mode) t hsdicnv 0 ns sck valid setup time from cnv rising edge (chain mode) t ssckcnv 5 ns sck valid hold time from cnv rising edge (chain mode) t hsckcnv 5 ns sdi valid setup time from sck falling edge (chain mode) t ssdisck 3 ns sdi valid hold time from sck falling edge (chain mode) t hsdisck 4 ns sdi high to sdo high (chain mode with busy indicator) t dsdosdi vio above 4.5 v 15 ns vio above 2.3 v 26 ns
ad7688 rev. a | page 6 of 28 absolute maximum ratings stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 5. parameter rating analog inputs in+ 1 , in? 1 gnd ? 0.3 v to vdd + 0.3 v or 130 ma ref gnd ? 0.3 v to vdd + 0.3 v supply voltages vdd, vio to gnd ?0.3 v to +7 v vdd to vio 7 v digital inputs to gnd ?0.3 v to vio + 0.3 v digital outputs to gnd ?0.3 v to vio + 0.3 v storage temperature range ?65c to +150c junction temperature 150c lead temperature range jedec j-std-20 thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 6. thermal resistance package type ja jc unit 10-lead qfn (lfcsp) 48.7 2.96 c 10-lead msop 200 44 c 1 see the analog input section. esd caution 500ai ol 500ai oh 1.4v to sdo c l 50pf 02973-003 figure 3. load circuit fo r digital interface timing 30% vio 70% vio 2v or vio ? 0.5v 1 0.8v or 0.5v 2 0.8v or 0.5v 2 2v or vio ? 0.5v 1 t delay t delay 02973-004 1 2v if vio above 2.5v, vio ? 0.5v if vio below 2.5v. 2 0.8v if vio above 2.5v, 0.5v if vio below 2.5v. figure 4. voltage levels for timing
ad7688 rev. a | page 7 of 28 pin configuration and fu nction descriptions 02973-005 ref 1 vdd 2 in+ 3 in? 4 gnd 5 vio 10 sdi 9 sck 8 sdo 7 cnv 6 ad7688 top view (not to scale) figure 5. 10-lead ms op pin configuration 02973-006 1 ref 2 vdd 3 in+ 4 in? 5 gnd 10 vio 9sdi 8sck 7sdo 6 cnv notes 1. for the lfcsp package only, the exposed paddle must be connected to gnd. top view (not to scale) ad7688 figure 6. 10-lead qfn (l f csp ) pin configuration table 7. pin function descriptions pin no. mnemonic type 1 function 1 ref ai reference input voltage. the ref range is from 0.5 v to vdd. it is referred to the gnd pin. this pin should be decoupled closely to the pin with a 10 f capacitor. 2 vdd p power supply. 3 in+ ai differential positive analog input. 4 in? ai differential negative analog input. 5 gnd p power supply ground. 6 cnv di convert input. this input has multiple functions. on its leading edge, it initiates the conversions and selects the interface mode, chain or cs . in cs mode, it enables the sdo pin when low. in chain mode, the data should be read when cnv is high. 7 sdo do serial data output. the conversion result is output on this pin. it is synchronized to sck. 8 sck di serial data clock input. when the part is select ed, the conversion result is shifted out by this clock. 9 sdi di serial data input. this input provides multiple fe atures. it selects the interface mode of the adc as follows: chain mode is selected if sdi is low during the cnv risi ng edge. in this mode, sdi is used as a data input to daisy-chain the conversion results of two or more adcs onto a single sdo line. the digital data level on sdi is output on sdo with a delay of 16 sck cycles. cs mode is selected if sdi is high during the cnv risi ng edge. in this mode, either sdi or cnv can enable the serial output signals when low, and if sdi or cnv is low when the conversion is complete, the busy indicator feature is enabled. 10 vio p input/output interface digital power. nominally at the same supply as the host interface (1.8 v, 2.5 v, 3 v, or 5 v). epad n/a for the lfcsp package only, the exposed paddle must be connected to gnd. 1 ai = analog input, di = digital input, do = dig ital output, p = power, and n/a = not applicable.
ad7688 rev. a | page 8 of 28 terminology integral nonlinearity error (inl) it refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs ? lsb before the first code transition. positive full scale is defined as a level 1? lsb beyond the last code transition. the deviation is measured from the middle of each code to the true straight line ( figure 25 ). differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. dnl is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. zero error it is the difference between the ideal midscale voltage, that is, 0 v, from the actual voltage producing the midscale output code, that is, 0 lsb. gain error the first transition (from 100 . . . 00 to 100 . . . 01) should occur at a level ? lsb above nominal negative full scale (?4.999924 v for the 5 v range). the last transition (from 01110 to 01111) should occur for an analog voltage 1? lsb below the nominal full scale (+4.999771 v for the 5 v range.) the gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. spurious-free dynamic range (sfdr) sfdr is the difference, in decibels (db), between the rms amplitude of the input signal and the peak spurious signal. effective number of bits (enob) enob is a measurement of the resolution with a sine wave input. it is related to s/(n+d) by the following formula enob = ( s/[ n + d ] db ? 1.76)/6.02 and is expressed in bits. total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in db. dynamic range it is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together. the value for dynamic range is expressed in db. signal-to-noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in db. signal-to-(noise + distortion) ratio (s/[n+d]) s/(n+d) is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for s/(n+d) is expressed in db. aperture delay aperature delay is the measure of the acquisition performance. it is the time between the rising edge of the cnv input and when the input signal is held for a conversion. transient resp onse it is the time required for the adc to accurately acquire its input after a full-scale step function was applied.
ad7688 rev. a | page 9 of 28 typical performance characteristics code inl (lsb) 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 0 16384 32768 49152 65535 02973-001 positive inl = +0.31lsb negative inl = ?0.39lsb figure 7. integral nonlinearity vs. code 02973-007 counts 300000 250000 150000 200000 100000 50000 0 code in hex 73 74 75 6f 70 71 72 0 0 2930 0 0 256159 2031 vdd = ref = 5v figure 8. histogram of a dc input at the code center frequency (khz) amplitude (db of full scale) 0 ?20 ?40 ?60 ?80 ?100 ?120 ?160 ?140 ?180 0 25 50 75 100 125 150 200175 225 250 02973-008 16384 point fft vdd = ref = 5v f s = 500ksps f in = 2khz snr = 95.6db thd = ?117.7db sfdr = ?117.9db 2nd harm = ?125db 3rd harm = ?119db figure 9. fft plot code dnl (lsb) 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 0 16384 32768 49152 65535 02973-009 positive dnl = +0.37lsb negative dnl = ?0.21lsb figure 10. differential nonlinearity vs. code 02973-010 counts 160000 120000 140000 100000 80000 40000 20000 60000 0 code in hex 74 76 71 73 0 72 0 75 00 136187 124933 vdd = ref = 5v figure 11. histogram of a dc input at the code transition 02973-011 input level (db) 0 ?10?8?6?4?2 snr (db) 100 99 98 97 96 95 94 93 92 91 90 figure 12. snr vs. input level
ad7688 rev. a | page 10 of 28 02973-012 reference voltage (v) 5.5 2.3 2.7 3.5 4.3 5.1 3.1 3.9 4.7 snr, s/(n + d) (db) 100 95 85 90 70 snr enob enob (bits) 17.0 15.0 16.0 14.0 13.0 s/[n + d] figure 13. snr, s/(n + d), and enob vs. reference voltage 02973-013 temperature ( c) 125 ?55 ?35 ?15 5 25 45 65 85 105 snr (db) 100 95 90 85 80 vref = 5v figure 14. snr vs. temperature 02973-014 frequency (khz) 200 0 50 100 150 s/(n + d) (db) 100 95 85 90 80 75 70 vref = 5v, ?10db vref = 5v, ?1db figure 15. s/(n + d) vs. frequency 02973-015 reference voltage (v) 5.5 2.3 2.7 3.5 4.3 5.1 3.1 3.9 4.7 thd, sfdr (db) ?100 ?110 ?105 ?115 ?120 ?125 ?130 sfdr thd figure 16. thd, sfdr vs. reference voltage 02973-016 temperature ( c) 125 ?55 ?35 ?15 5 25 45 65 85 105 thd (db) ?90 ?100 ?110 ?120 ?130 vref = 5v figure 17. thd vs. temperature 02973-017 frequency (khz) 200 0 50 100 150 thd (db) ?60 ?70 ?90 ?80 ?100 ?110 ?120 vref = 5v, ?10db vref = 5v, ?1db figure 18. thd vs. frequency
ad7688 rev. a | page 11 of 28 supply (v) operating current ( a) 1000 750 500 250 0 4.50 4.75 5.00 5.25 5.5 02973-018 vio vdd f s = 100ksps figure 19. operating currents vs. supply temperature ( c) power-down current (na) 1000 750 500 250 0 ?55 ?35 ?15 5 25 45 65 85 105 125 02973-019 vdd + vio figure 20. power-down currents vs. temperature temperature ( c) operating current ( a) 1000 750 500 250 0 ?55 ?35 ?15 5 25 45 65 85 105 125 02973-020 vio vdd f s = 100ksps figure 21. operating currents vs. temperature 02973-021 temperature ( c) 125 ?55 ?35 ?15 5 25 45 65 85 105 offset, gain error (lsb) 6 4 2 0 ?2 ?4 ?6 gain error offset error figure 22. offset and gain error vs. temperature 02973-022 sdo capacitive load (pf) 120 0 20406080100 t dsdo delay (ns) 25 20 15 10 5 0 vdd = 5v, 85c vdd = 5v, 25c figure 23. t dsdo delay vs. capacitance load and supply
ad7688 rev. a | page 12 of 28 sw+ msb 16,384c in+ lsb comp control logic switches control busy output code cnv ref gnd in? 4c 2c c c 32,768c sw? msb 16,384c lsb 4c 2c c c 32,768c 02973-023 figure 24. adc simplified schematic circuit information the ad7688 is a fast, low power, single-supply, precise 16-bit adc using a successive approximation architecture. the ad7688 is capable of converting 500,000 samples per second (500 ksps) and powers down between conversions. when operating at 100 sps, for example, it consumes 3.75 w typically, ideal for battery-powered applications. the ad7688 provides the user with an on-chip track-and-hold and does not exhibit any pipeline delay or latency, making it ideal for multiple multiplexed channel applications. the ad7688 is specified from 4.5 v to 5.5 v and can be interfaced to any of the 1.8 v to 5 v digital logic family. it is housed in a 10-lead msop or a tiny 10-lead qfn ( lfcsp) that combines space savings and allows flexible configurations. it is pin-for-pin-compatible with the ad7685, ad7686 , and ad7687. converter operation the ad7688 is a successive approximation adc based on a charge redistribution dac. figure 24 shows the simplified schematic of the adc. the capacitive dac consists of two identical arrays of 16 binary weighted capacitors, which are connected to the two comparator inputs. during the acquisition phase, terminals of the array tied to the comparators input are connected to gnd via sw+ and sw?. all independent switches are connected to the analog inputs. thus, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the in+ and in? inputs. when the acquisition phase is complete and the cnv input goes high, a conversion phase is initiated. when the conversion phase begins, sw+ and sw? are opened first. the two capacitor arrays are then disconnected from the inputs and connected to the gnd input. therefore, the differential voltage between the inputs in+ and in? captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. by switching each element of the capacitor array between gnd and ref, the comparator input varies by binary weighted voltage steps (v ref /2, v ref /4 . . . v ref /65536). the control logic toggles these switches, starting with the msb, in order to bring the comparator back into a balanced condition. after the completion of this process, the part returns to the acquisition phase and the control logic generates the adc output code and a busy signal indicator. because the ad7688 has an on-board conversion clock, the serial clock, sck, is not required for the conversion process.
ad7688 rev. a | page 13 of 28 transfer functions the ideal transfer characteristic for the ad7688 is shown in figure 25 and table 8 . 100...000 100...001 100...010 011...101 011...110 011...111 adc code (twos complement) analog input +fsr ? 1.5 lsb +fsr ? 1 lsb ?fsr + 1 lsb ?fsr ?fsr + 0.5 lsb 02973-024 figure 25. adc ideal transfer function table 8. output codes and ideal input voltages description analog input v ref 5 v digital output code hea fsr C 1 lsb +4.999847 v 7fff 1 midscale + 1 lsb +152.6 v 0001 midscale 0 v 0000 midscale C 1 lsb ?152.6 v ffff Cfsr + 1 lsb ?4.999847 v 8001 Cfsr ?5 v 8000 2 typical connection diagram figure 26 shows an example of the recommended connection diagram for the ad7688 when multiple supplies are available. 1. this is also the code for an overranged analog input (v in+ ? v in? above v ref ? v gnd ). 2. this is also the code for an underranged analog input (v in+ ? v in? below ?v ref + v gnd ). ad7688 ref gnd vdd in? in+ vio sdi sck sdo cnv 3- or 4-wire interface 5 100nf 100nf 5v 10 f 2 7v 7v ?2v 1.8v to vdd ref 1 0 to vref 33 2.7nf 3 4 7v ?2v vref to 0 33 2.7nf 3 4 02973-025 1 see reference section for reference selection. 2 c ref is usually a 10 f ceramic capacitor (x5r). 3 see driver amplifier choice section. 4 optional filter. see analog input section. 5 see digital interface for most convenient interface mode. figure 26. typical application diagram with multiple supplies
ad7688 rev. a | page 14 of 28 analog input figure 27 shows an equivalent circuit of the input structure of the ad7688. the two diodes, d1 and d2, provide esd protection for the analog inputs in+ and in?. care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0.3 v because this causes these diodes to begin to forward- bias and start conducting current. these diodes can handle a forward-biased current of 130 ma maximum. for instance, these conditions could eventually occur when the input buffers (u1) supplies are different from vdd. in such a case, an input buffer with a short-circuit current limitation can be used to protect the part. c in r in d1 d2 c pin in+ or in? gnd vdd 02973-026 figure 27. equivalent analog input circuit the analog input structure allows the sampling of the true differential signal between in+ and in?. by using these differential inputs, signals common to both inputs are rejected, as shown in figure 28 , which represents the typical cmrr over frequency. 02973-027 frequency (khz) 10000 1 10 100 1000 cmrr (db) 80 70 60 vdd = 5v figure 28. analog input cmrr vs. frequency during the acquisition phase, the impedance of the analog inputs (in+ or in?) can be modeled as a parallel combination of capacitor, c pin , and the network formed by the series connection of r in and c in . c pin is primarily the pin capacitance. r in is typically 600 and is a lumped component made up of some serial resistors and the on resistance of the switches. c in is typically 30 pf and is mainly the adc sampling capacitor. during the conversion phase, where the switches are opened, the input impedance is limited to c pin . r in and c in make a 1-pole, low-pass filter that reduces undesirable aliasing effects and limits the noise. when the source impedance of the driving circuit is low, the ad7688 can be driven directly. large source impedances significantly affect the ac performance, especially total harmonic distortion (thd). the dc performances are less sensitive to the input impedance. the maximum source impedance depends on the amount of thd that can be tolerated. the thd degrades as a function of the source impedance and the maximum input frequency, as shown in figure 29 . frequency (khz) thd (db) ?60 ?70 ?80 ?90 ?100 ?110 ?120 0 25 50 75 100 02973-028 r s = 250 r s = 100 r s = 50 r s = 33 figure 29. thd vs. analog input frequency and source resistance
ad7688 rev. a | page 15 of 28 d river amplifier choice although the ad7688 is easy to drive, the driver amplifier needs to meet the following requirements: ? the noise generated by the driver amplifier needs to be kept as low as possible in order to preserve the snr and transition noise performance of the ad7688. note that the ad7688 has a noise much lower than most of the other 16-bit adcs and, therefore, can be driven by a noisier op amp while preserving the same or better system perform- ance. the noise coming from the driver is filtered by the ad7688 analog input circuit 1-pole, low-pass filter made by r in and c in or by the external filter, if one is used. because the typical noise of the ad7688 is 53 v rms, the snr degradation due to the amplifier is ? ? ? ? ? ? ? ? ? ? ? ? ? ? + = ? 2 2 )( 2 5 53 20log n 3db loss nef snr 3 where: f C3db is the input bandwidth in mhz of the ad7688 (9 mhz) or the cutoff frequency of the input filter, if one is used. n is the noise gain of the amplifier (for example, +1 in buffer configuration). e n is the equivalent input noise voltage of the op amp, in nv/hz. ? for ac applications, the driver should have a thd performance commensurate with the ad7688. figure 18 shows the thd vs. frequency that the driver should exceed. ? for multichannel multiplexed applications, the driver amplifier and the ad7688 analog input circuit must settle for a full-scale step onto the capacitor array at a 16-bit level (0.0015%, 15 ppm). in the amplifiers data sheet, settling at 0.1% to 0.01% is more commonly specified. this could differ significantly from the settling time at a 16-bit level and should be verified prior to driver selection. table 9. recommended driver amplifiers amplifier typical application ad8021 very low noise and high frequency ad8022 low noise and high frequency op184 low power, low noise, and low frequency ad8605 , ad8615 5 v single-supply, low power ad8519 small, low power and low frequency ad8031 high frequency and low power single-to-differ ential driver for applications using a single-ended analog signal, either bipolar or unipolar, a single-ended-to-differential driver allows for a differential input into the part. the schematic is shown in figure 30 . when provided a single-ended input signal, this configuration produces a differential v ref with midscale at v ref /2. u2 10k 590 ad7688 in+ in? ref u1 analog input ( 10v, 5v, ..) 590 10 f 100nf 10k vref vref 590 100nf vref 02973-029 figure 30. single-ended-to-di fferential driver circuit voltage reference input the ad7688 voltage reference input, ref, has a dynamic input impedance and should therefore be driven by a low impedance source with efficient decoupling between the ref and gnd pins, as explained in the layout section. when ref is driven by a very low impedance source, for example, a reference buffer using the ad8031 or the ad8605, a 10 f (x5r, 0805 size) ceramic chip capacitor is appropriate for optimum performance. if an unbuffered reference voltage is used, the decoupling value depends on the reference used. for instance, a 22 f (x5r, 1206 size) ceramic chip capacitor is appropriate for optimum performance using a low temperature drift adr43x reference. if desired, smaller reference decoupling capacitor values down to 2.2 f can be used with a minimal impact on performance, especially dnl. regardless, there is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nf) between the ref and gnd pins. power supply the ad7688 is specified at 4.5 v to 5.5 v. it has, unlike other low voltage converters, a low enough noise to design a 16-bit resolution system with low supply and respectable performance. it uses two power supply pins: a core supply vdd and a digital input/output interface supply vio. vio allows direct interface with any logic between 1.8 v and vdd. to reduce the supplies needed, the vio and vdd can be tied together. the ad7688 is independent of power supply sequencing between vio and vdd. additionally, it is very insensitive to power supply variations over a wide frequency range, as shown in figure 31 , which represents psrr over frequency.
ad7688 rev. a | page 16 of 28 02973-030 frequency (khz) 10000 1 1000 10 100 psrr (db) 95 90 85 80 75 70 65 60 figure 31. psrr vs. frequency the ad7688 powers down automatically at the end of each conversion phase and, therefore, the power scales linearly with the sampling rate, as shown in figure 32 . this makes the part ideal for low sampling rate (even a few hz) and low battery- powered applications. sampling rate (sps) operating current ( a) 1000 10 0.1 0.001 10 100 1000 10000 100000 1000000 02973-031 vio vdd figure 32. operating currents vs. sampling rate s upplying the adc from the reference f or simplified applications, the ad7688, with its low operating current, can be supplied directly using the reference circuit shown in figure 33 . the reference line can be driven by either: ? the system power supply directly. ? a reference voltage with enough current output capability, such as the adr43x. ? a reference buffer, such as the ad8031, which can also filter the system power supply, as shown in figure 33 . ad8031 ad7688 vio ref vdd 10 f 1 f 10 10k 5v 5v 5v 1 f 1 02973-032 1 optional reference buffer and filter. figure 33. example of application circuit digital interface though the ad7688 has a reduced number of pins, it offers flexibility in its serial interface modes. the ad7688, when in cs mode, is compatible with spi, qspi, digital hosts, and dsps, e.g., blackfin? adsp-bf53x or adsp- 219x. this interface can use either 3-wire or 4-wire. a 3-wire interface using the cnv, sck, and sdo signals minimizes wiring connections useful, for instance, in isolated applications. a 4-wire interface using the sdi, cnv, sck, and sdo signals allows cnv, which initiates the conversions, to be independent of the readback timing (sdi). this is useful in low jitter sampling or simultaneous sampling applications. the ad7688, when in chain mode, provides a daisy chain feature using the sdi input for cascading multiple adcs on a single data line similar to a shift register. the mode in which the part operates depends on the sdi level when the cnv rising edge occurs. the cs mode is selected if sdi is high and the chain mode is selected if sdi is low. the sdi hold time is such that when sdi and cnv are connected together, the chain mode is always selected. in either mode, the ad7688 offers the flexibility to optionally force a start bit in front of the data bits. this start bit can be used as a busy signal indicator to interrupt the digital host and trigger the data reading. otherwise, without a busy indicator, the user must time out the maximum conversion time prior to readback. the busy indicator feature is enabled as: ? in the cs mode, if cnv or sdi is low when the adc conversion ends ( and ). figure 37 figure 41 ? in the chain mode, if sck is high during the cnv rising edge ( figure 45 ).
ad7688 rev. a | page 17 of 28 cs mode 3-wire, no busy indicator this mode is usually used when a single ad7688 is connected to an spi-compatible digital host. the connection diagram is shown in figure 34 and the corresponding timing is given in figure 35 . with sdi tied to vio, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. once a conversion is initiated, it continues to completion irrespective of the state of cnv. for instance, it could be useful to bring cnv low to select other spi devices, such as analog multiplexers, but cnv must be returned high before the minimum conversion time and held high until the maximum conversion time to avoid the generation of the busy signal indicator. when the conversion is complete, the ad7688 enters the acquisition phase and powers down. when cnv goes low, the msb is output onto sdo. the remaining data bits are then clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate provided it has an acceptable hold time. after the 16th sck falling edge or when cnv goes high, whichever is earlier, sdo returns to high impedance. cnv sck sdo sdi data in clk convert v io digital host ad7688 02973-033 figure 34. cs mode 3-wire, no busy indicator connection diagram (sdi high) sdo d15 d14 d13 d1 d0 t dis sck 1 2 3 14 15 16 t sck t sckl t sckh t hsdo t dsdo cnv conversion acquisition t conv t cyc acquisition sdi = 1 t cnvh t acq t en 02973-034 figure 35. cs mode 3-wire, no busy indicator serial interface timing (sdi high)
ad7688 rev. a | page 18 of 28 cs mode 3-wire with busy indicator this mode is usually used when a single ad7688 is connected to an spi-compatible digital host having an interrupt input. the connection diagram is shown in figure 36 and the corresponding timing is given in figure 37 . with sdi tied to vio, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. sdo is maintained in high impedance until the completion of the conversion irrespective of the state of cnv. prior to the minimum conversion time, cnv could be used to select other spi devices, such as analog multiplexers, but cnv must be returned low before th e minimum conversion time and held low until the maximum conversion time to guarantee the generation of the busy signal indicator. when the conversion is complete, sdo goes from high impedance to low. with a pull-up on the sdo line, this transition can be used as an interrupt signal to initiate the data reading controlled by the digital host. the ad7688 then enters the acquisition phase and powers down. the data bits are then clocked out, msb first, by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate provided it has an acceptable hold time. after the optional 17th sck falling edge, or when cnv goes high, whichever is earlier, sdo returns to high impedance. if multiple ad7688s are selected at the same time, the sdo output pin handles this contention without damage or induced latch-up. meanwhile, it is recommended to keep this contention as short as possible to limit extra power dissipation. data in irq clk convert vio digital host 02973-035 47k cnv sck sdo sdi v io ad7688 figure 36. cs mode 3-wire with busy indicator connection diagram (sdi high) sdo d15 d14 d1 d0 t dis sck 123 151617 t sck t sckl t sckh t hsdo t dsdo cnv conversion acquisition t conv t cyc t cnvh t acq acquisition sdi = 1 02973-036 figure 37. cs mode 3-wire with busy indicator serial interface timing (sdi high)
ad7688 rev. a | page 19 of 28 cs mode 4-wire, no busy indicator this mode is usually used when multiple ad7688s are connected to an spi-compatible digital host. a connection diagram example using two ad7688s is shown in figure 38 and the corresponding timing is given in figure 39 . with sdi high, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. in this mode, cnv must be held high during the conversion phase and the subsequent data readback (if sdi and cnv are low, sdo is driven low). prior to the minimum conversion time, sdi could be used to select other spi devices, such as analog multiplexers, but sdi must be returned high before the minimum conversion time and held high until the maximum conversion time to avoid the generation of the busy signal indicator. when the conversion is complete, the ad7688 enters the acquisition phase and powers down. each adc result can be read by bringing low its sdi input which consequently outputs the msb onto sdo. the remaining data bits are then clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate provided it has an acceptable hold time. after the 16th sck falling edge, or when sdi goes high, whichever is earlier, sdo returns to high impedance and another ad7688 can be read. data in clk cs1 convert cs2 digital host 02973-037 cnv sck sdo sdi ad7688 cnv sck sdo sdi ad7688 figure 38. cs mode 4-wire, no busy in dicator connection diagram sdo d15 d14 d13 d1 d0 t dis sck 123 303132 t hsdo t dsdo t en conversion acquisition t conv t cyc t acq acquisition sdi(cs1) cnv t ssdicnv t hsdicnv d1 14 15 t sck t sckl t sckh d0 d15 d14 17 18 16 sdi(cs2) 02973-038 figure 39. cs mode 4-wire, no busy indicator serial interface timing
ad7688 rev. a | page 20 of 28 cs mode 4-wire with busy indicator this mode is usually used when a single ad7688 is connected to an spi-compatible digital host, which has an interrupt input, and it is desired to keep cnv, which is used to sample the analog input, independent of the signal used to select the data reading. this requirement is particularly important in applications where low jitter on cnv is desired. the connection diagram is shown in figure 40 and the corresponding timing is given in figure 41 . with sdi high, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. in this mode, cnv must be held high during the conversion phase and the subsequent data readback (if sdi and cnv are low, sdo is driven low). prior to the minimum conversion time, sdi could be used to select other spi devices, such as analog multiplexers, but sdi must be returned low before the minimum conversion time and held low until the maximum conversion time to guarantee the generation of the busy signal indicator. when the conversion is complete, sdo goes from high impedance to low. with a pull-up on the sdo line, this transition can be used as an interrupt signal to initiate the data readback controlled by the digital host. the ad7688 then enters the acquisition phase and powers down. the data bits are then clocked out, msb first, by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate provided it has an acceptable hold time. after the optional 17th sck falling edge, or sdi going high, whichever is earlier, the sdo returns to high impedance. data in irq clk convert cs1 vio digital host 02973-039 47k cnv sck sdo sdi ad7688 figure 40. cs mode 4-wire with busy indicator connection diagram sdo d15 d14 d1 d0 t dis sck 123 151617 t sck t sckl t sckh t hsdo t dsdo t en conversion a cquisition t conv t cyc t acq acquisition sdi cnv t ssdicnv t hsdicnv 02973-040 figure 41. cs mode 4-wire with busy indicator serial interface timing
ad7688 rev. a | page 21 of 28 chain mode, no busy indicator this mode can be used to daisy-chain multiple ad7688s on a 3- wire serial interface. this feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. data readback is analogous to clocking a shift register. a connection diagram example using two ad7688s is shown in figure 42 and the corresponding timing is given in figure 43 . when sdi and cnv are low, sdo is driven low. with sck low, a rising edge on cnv initiates a conversion, selects the chain mode, and disables the busy indicator. in this mode, cnv is held high during the conversion phase and the subsequent data readback. when the conversion is complete, the msb is output onto sdo and the ad7688 enters the acquisition phase and powers down. the remaining data bits stored in the internal shift register are then clocked by subsequent sck falling edges. for each adc, sdi feeds the input of the internal shift register and is clocked by the sck falling edge. each adc in the chain outputs its data msb first, and 16 n clocks are required to readback the n adcs. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate and, consequently more ad7688s in the chain, provided the digital host has an acceptable hold time. the maximum conversion rate may be reduced due to the total readback time. for instance, with a 3 ns digital host set-up time and 3 v interface, up to four ad7688s running at a conversion rate of 360 ksps can be daisy-chained on a 3-wire port. clk convert data in digital host 02973-041 cnv sck sdo sdi ad7688 b cnv sck sdo sdi ad7688 a figure 42. chain mode, no busy indicator connection diagram s do a = sdi b d a 15 d a 14 d a 13 sck 1 2 3 30 31 32 t ssdisck t hsdisc t en conversion acquisition t conv t cyc t acq acquisition cnv d a 1 14 15 t sck t sckl t sckh d a 0 17 18 16 sdi a = 0 sdo b d b 15 d b 14 d b 13 d a 1 d b 1d b 0d a 15 d a 14 t hsdo t dsdo t ssckcnv t hsckcnv d a 0 02973-042 figure 43. chain mode, no busy indicator serial interface timing
ad7688 rev. a | page 22 of 28 chain mode with busy indicator this mode can also be used to daisy-chain multiple ad7688s on a 3-wire serial interface while providing a busy indicator. this feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. data readback is analogous to clocking a shift register. a connection diagram example using three ad7688s is shown in figure 44 and the corresponding timing is given in figure 45 . when sdi and cnv are low, sdo is driven low. with sck high, a rising edge on cnv initiates a conversion, selects the chain mode, and enables the busy indicator feature. in this mode, cnv is held high during the conversion phase and the subsequent data readback. when all adcs in the chain have completed their conversions, the nearend adc (adc c in figure 44 ) sdo is driven high. this transition on sdo can be used as a busy indicator to trigger the data readback controlled by the digital host. the ad7688 then enters the acquisition phase and powers down. the data bits stored in the internal shift register are then clocked out, msb first, by subsequent sck falling edges. for each adc, sdi feeds the input of the internal shift register and is clocked by the sck falling edge. each adc in the chain outputs its data msb first, and 16 n + 1 clocks are required to readback the n adcs. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate and consequently more ad7688s in the chain, provided the digital host has an acceptable hold time. for instance, with a 3 ns digital host setup time and 3 v interface, up to four ad7688s running at a conversion rate of 360 ksps can be daisy-chained to a single 3-wire port. clk convert data in irq digital host 02973-043 cnv sck sdo sdi ad7688 c cnv sck sdo sdi ad7688 a cnv sck sdo sdi ad7688 b figure 44. chain mode with bu sy indicator connection diagram sdo a = sdi b d a 15 d a 14 d a 13 sck 123 35 47 48 t en conversion a cquisition t conv t cyc t acq acquisition cnv = sdi a d a 1 415 t sck t sckh t sckl d a 0 17 34 16 sdo b = sdi c d b 15 d b 14 d b 13 d a 1 d b 1d b 0d a 15 d a 14 49 t ssdisck t hsdisc t hsdo t dsdo sdo c d c 15 d c 14 d c 13 d a 1d a 0 d c 1d c 0d a 14 19 31 32 18 33 d b 1d b 0d a 15 d b 15 d b 14 t dsdosdi t ssckcnv t hsckcnv 02973-044 d a 0 t dsdosdi t dsdosdi t dsdosdi t dsdosdi figure 45. chain mode with busy indicator serial interface timing
ad7688 rev. a | page 23 of 28 application hints layout the printed circuit board that houses the ad7688 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. the pinout of the ad7688, with all its analog signals on the left side and all its digital signals on the right side, eases this task. avoid running digital lines under the device because these couple noise onto the die, unless a ground plane under the ad7688 is used as a shield. fast switching signals, such as cnv or clocks, should never run near analog signal paths. crossover of digital and analog signals should be avoided at least one ground plane should be used. it could be common or split between the digital and analog sections. in the latter case, the planes should be joined underneath the ad7688s. the ad7688 voltage reference input ref has a dynamic input impedance and should be decoupled with minimal parasitic inductances. this is done by placing the reference decoupling ceramic capacitor close to, and ideally right up against, the ref and gnd pins and connecting it with wide, low impedance traces. finally, the power supplies vdd and vio of the ad7688 should be decoupled with ceramic capacitors (typically 100 nf) placed close to the ad7688 and connected using short and wide traces to provide low impedance paths and reduce the effect of glitches on the power supply lines. an example of layout following these rules is shown in figure 46 and figure 47 . evaluating the ad7688s performance other recommended layouts for the ad7688 are outlined in the documentation of the evaluation board for the ad7688 ( eval-ad7688 ). the evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a pc via the eval-control brd3. 02973-045 figure 46. example of layout of the ad7688 (top layer) 02973-046 figure 47. example of layout of the ad7688 (bottom layer)
ad7688 rev. a | page 24 of 28 outline dimensions compliant to jedec standards mo-187-ba 091709-a 6 0 0.70 0.55 0.40 5 10 1 6 0.50 bsc 0.30 0.15 1.10 max 3.10 3.00 2.90 coplanarity 0.10 0.23 0.13 3.10 3.00 2.90 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 figure 48.10-lead mini small outline package [msop] (rm-10) dimensions shown in millimeters 2.48 2.38 2.23 0.50 0.40 0.30 121009-a top view 10 1 6 5 0.30 0.25 0.20 bottom view pin 1 index area seating plane 0.80 0.75 0.70 1.74 1.64 1.49 0.20 ref 0.05 max 0.02 nom 0.50 bsc exposed pad 3.10 3.00 sq 2.90 p i n 1 i n d i c a t o r ( r 0 . 1 5 ) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 49. 10-lead lead frame chip scale package [qfn (lfcsp_wd)] 3 mm 3 mm body, very very thin, dual lead (cp-10-9) dimensions shown in millimeters
ad7688 rev. a | page 25 of 28 ordering guide model 1 , 2 , 3 integral nonlinearity temperature range transport media, quantity package description package option branding ad7688brmz 1.5 lsb max C40c to +85c tube, 50 10-lead msop rm-10 c3k ad7688brmzrl7 1.5 lsb max C40c to +85c reel, 1,000 10-lead msop rm-10 c3k ad7688bcpzrl 1.5 lsb max C40c to +85c reel, 5,000 10-lead qfn (lfcsp_wd) cp-10-9 #c04 ad7688bcpzrl7 1.5 lsb max C40c to +85c reel, 1,500 10-lead qfn (lfcsp_wd) cp-10-9 #c04 eval-ad7688cbz evaluation board eval-control brd2z controller board eval-control brd3z controller board 1 z = rohs compliant part, # denotes rohs compliant product, may be top or bottom marked. 2 the eval-ad7688cb can be used as a standalone evaluati on board or in conjunction with the eval-control brdx for evaluation/dem onstration purposes. 3 the eval-control brd2 and eval-control brd3 allow a pc to control and communicate with all analog devices evaluation boards en ding in the cb designators.
ad7688 rev. a | page 26 of 28 notes
ad7688 rev. a | page 27 of 28 notes
ad7688 rev. a | page 28 of 28 notes ?2007C2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d02973-0-2/11(a)

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